- ZBNF syntax descr

JZtxtcmd / Zmake

- main description

- Zmake

Docu Generation


Text/XML conversion

embedded multiplatform C



- -Dependencies

- -QuellcodeGenerierung

Inspector & Reflection

- Test on Runtime

- The inspector tool

- Reflection in C

- Inspector Communication

Graphical Programming

Model based - Modelica

Model based - Simulink

SPE SinglePairEthernet


Download Page


SPE Single Pair Ethernet 10Baset-T1L for fast step times 50 µs

SpeA-Videos Some videos to show usage and approaches

SpeA-Manual description

SpeA-ControllerSw description

SpeA-Board description

SpeA-FPGA functions and description

It is a simple connection for field communication, it can be become a really common standard for field busses till the end points of control (measurements and actuators), including power supply over data line.

This page shows a contribution for fast time deterministic communication.


Ring topology

For long distances: 10 Mbit/s, though fast cycle till 50 µs


Cycle time synchronization

Dedicated delay and less jitter between receive and forward transmit in the ring or for switches, the SFD is the synchronization point.
All controllers can be synchronized in interrupt execution and PWM ("Pulse Width Modulation") phase to a common cycle using SFD synchronization (with PLL, "Phase Look Loop")

SFD = "Start Frame Delimiter", left cursor is on SFD of the blue channel, right on red.

The Sync-Phase in the telegram is used to synchronize the clocks in all stations.



Data just in time, fast access

The data between SPE adapter and controller are transferred via SPI (Serial Peripheral Interface). They are read and written via DMA (Direct Memory Access) from and to the controller RAM, immediately a less time before transmit and after receive. With that approach the dead time for closed loop applications can be reduces. Watch the explanation and then the video linked there.


An evaluation board with FPGA and SPI access to controller